1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which accepts serial data in synchronization with a clock signal and writes the data in a memory cell as parallel data. In particular, the present invention relates to a technique for performing a write operation at higher speed.
2. Description of the Related Art
These kinds of semiconductor integrated circuits having been developed include FCRAMs (Fast Cycle RAMs). FCRAMs are divided into two types. One type has an SDRAM like (Synchronous DRAM) interface for accepting data in synchronization with the rises of a single-phase clock signal. The other has a DDR SDRAM like (Double Data Rate SDRAM) interface for accepting serial data in synchronization with the respective rises of complementary clock signals (or in synchronization with both the rises and falls of a single-phase clock signal). The general outlines of FCRAMs are described in NIKKEI ELECTRONICS 1998.6.15 (no. 718), Nikkei business publications.
FIG. 1 shows the main parts associated with a write operation in the FCRAM with an SDRAM like interface. The FCRAM has an input controlling unit 1, a core timing controlling unit 2, a core controlling signal generating unit 3, and a memory core unit 4 as the circuit associated with the write operation.
The input controlling unit 1 has a clock buffer 5, an input buffer 6, a command decoder 7, an RASZ generator 8, a serial/parallel controlling circuit 9, a DQ buffer 10, and a serial/parallel conversion circuit 11.
The clock buffer 5 receives a clock signal CLK from the exterior, and outputs an internal clock signal ICLKZ. The input buffer 6 accepts a command signal CMD in synchronization with the internal clock signal ICLKZ, and outputs the accepted signal as an internal command signal ICMD. The command decoder 7 receives the internal command signal ICMD, decodes the command, and outputs a command activating signal ACTZ. The RASZ generator 8 receives the command activating signal ACTZ and a self-precharging signal SPRZ, and outputs a basic signal BRASZ for controlling circuit associated with row addressing. The serial/parallel controlling circuit 9 receives the internal clock signal ICLKZ, and outputs a write switching signal WSWZ. The DQ buffer 10 sequentially receives serial data signals DQ in synchronization with the internal clock signal ICLKZ and outputs the received signals as internal data signals DI0 and DI1. The serial/parallel conversion circuit 11 accepts the internal data signals DI0 and DI1 in synchronization with the write switching signal WSWZ and respectively outputs the accepted signals as common data signals CDB0Z and CDB1Z.
The core timing controlling unit 2 has a BLT activating timing generator 12, a word line activating timing generator 13, an SA activating timing generator 14, and a CL activating timing generator 15.
The BLT activating timing generator 12 receives the basic signal BRASZ , the write switching signal WSWZ, and a word line inactivating signal WLRZ, and outputs a bit line activating signal BLSZ and a bit line inactivating signal BLRZ. The word line activating timing generator 13 receives the bit line activating signal BLSZ and the basic signal BRASZ, and outputs a word line activating signal WLSZ and the word line inactivating signal WLRZ. The SA activating timing generator 14 receives the word line activating signal WLSZ and the word line inactivating signal WLRZ, and outputs a sense amplifier activating timing signal BLEZ. The CL activating timing generator 15 receives the sense amplifier activating timing signal BLEZ, and outputs a column line activating signal BCLZ and the self-precharging signal SPRZ.
The core controlling signal generating unit 3 has a BLT generator 16, a main-word decoder 17, a sense amplifier controller 18, and a column decoder 19.
The BLT generator 16 receives the bit line activating signal BLSZ and the bit line inactivating signal BLRZ, and outputs bit line controlling signals BLTX, BLTZ and a bit line controlling signal BRSX for precharging bit lines BL, /BL. The main-word decoder 17 receives the word line activating signal WLSZ and the word line inactivating signal WLRZ, and output a word line signal WLZ. The sense amplifier controller 18 receives the sense amplifier activating timing signal BLEZ, and outputs sense amplifier activating signals LEX and LEZ. The column decoder 19 receives the column line activating signal BCLZ, and outputs a column line signal CLZ.
The memory core unit 4 includes sense amplifiers 20, memory cells 21, and other components. The memory core unit 4 receives the bit line controlling signals BLTX, BLTZ, and BRSX, the word line signal WLZ, the sense amplifier activating signals LEX and LEZ, the column line signal CLZ, and the common data signals CDBOZ and CDB1Z.
Of the signals described above, those with trailing xe2x80x9czxe2x80x9d are positive logic signals, and those with trailing xe2x80x9cXxe2x80x9d are negative logic signals. Incidentally, address signals are omitted from FIG. 1. In actual device, the above-described circuits are activated in accordance with address signals, thereby selecting a predetermined memory cell.
FIG. 2 shows the main parts of the memory core unit 4.
The memory core unit 4 has plural pairs of complementary bit lines BL and /BL. The bit lines BL are connected with one another through nMOSs 4a and 4b. The bit lines /BL are connected with one another through nMOSs 4c and 4d. The bit lines BL and /BL are connected to nMOSs 4e and 4f for equalizing, nMOSs 4g and 4h for precharging, column switches 4i and 4j each consisting of an nMOS, a sense amplifier 20, and a memory cell 21.
The gates of the nMOSs 4a and 4c receive the bit line controlling signal BLTX. The gates of the nMOSs 4b and 4d receive the bit line controlling signal BLTZ. The gate of the nMOS 4e receives the bit line controlling signal BLTZ, and the gate of the nMOS 4f receives the bit line controlling signal BLTX.
Either the sources or the drains of the nMOSs 4g and 4h are connected to the bit lines BL and /BL, respectively. The others are connected to a precharging line VPR. The gates of the nMOSs 4g and 4h receive the bit line controlling signal BRSX.
Either the sources or the drains of the column switches 4i and 4j are connected to the bit lines BL and /BL, and the others are connected to data signals LDBX and LDBZ, respectively. The gates of the column switches 4i and 4j receive the column line signal CLZ. The data signals LDBX and LDBZ are complementary signals. The data signal LDBZ and the data signal LDBX carry the same logic as and the inverted logic from that of the common data signal CDB0Z, respectively. Other data signals LDBZ and LDBX (not shown) have the same logic as and the inverted logic from that of the common data signal CDB1Z, respectively.
The sense amplifier 20 has a CMOS inverter consisting of a PMOS 20a and an nMOS 20b, a CMOS inverter consisting of a pMOS 20c and an nMOS 20d, and a PMOS 20e and an nMOS 20f connected to the respective sources of the CMOS inverters to provide power supply thereto. The inputs and outputs of the CMOS inverters are connected to each other, and the respective outputs are connected to the bit lines /BL and BL. Either the source or the drain of the pMOS 20e is connected to the sources of the pMOS 20a and the pMOS 20c, and the other is connected to a power supply line VII. The gate of the pMOS 20e receives the sense amplifier activating signal LEX. Either the source or the drain of the NMOS 20f is connected to the sources of the nMOS 20b and the NMOS 20d, and the other is connected to a ground line VSS. The gate of the nMOS 20f receives the sense amplifier activating signal LEZ.
The memory cell 21 consists of an nMOS 21a for data transfer and a capacitor 21b. The gate of the nMOS 21a receives the word line signal WLZ.
Next, the operation of the above-described FCRAM will be explained.
FIG. 3 shows the timing of consecutive performance of write operations. In this example, two-bit serial data are being written consecutively.
In starting the write operation, a write command WR is supplied from the exterior. The input buffer 6 shown in FIG. 1 accepts the command signal CMD (the write command WR) in synchronization with the rise of the internal clock signal ICLKZ. The command decoder 7 receives the internal command signal ICMD, and activates the command activating signal ACTZ (FIG. 3(a)). The RASZ generator 8 receives the command activating signal ACTZ, and activates the basic signal BRASZ (FIG. 3(b)). The DQ buffer 10 sequentially accepts the data signals DQ in synchronization with the rises of the internal clock signal ICLKZ, and outputs the same in the form of the internal data signals DI0 and DI1 (FIG. 3(c)).
The serial/parallel controlling circuit 9 detects the rising edge of the internal clock signal ICLKZ after the reception of the write command WR, and activates the write switching signal WSWZ (FIG. 3(d)). The serial/parallel conversion circuit 11 accepts the internal data signals DI0 and DI1 in synchronization with the write switching signal WSWZ, executes serial/parallel conversion to the signals accepted, and output the converted data as the common data signals CDB0Z and CDB1Z (FIG. 3(e)).
The BLT activating timing generator 12 receives the activation of the write switching signal WSWZ, and activates the bit line activating signal BLSZ for a predetermined period (FIG. 3(f)). The BLT generator 16 receives the bit line activating signal BLSZ, and activates the bit line controlling signal BLTX and the bit line controlling signal BRSX (FIG. 3(g)). The equalization of the bit lines BL and /BL on the side closer to the memory cell 21 shown in FIG. 2 is terminated by the activation of the bit line controlling signal BLTX and the activation of the bit line controlling signal BLTZ, whereby the bit lines BL and /BL are connected to the sense amplifier 20. The bit lines BL and /BL on the side opposite from the memory cell 21 are equalized, and released from the connection with the sense amplifier 20. The activation of the bit line controlling signal BRSX resets the precharging operation to the bit lines BL and /BL.
The word line activating timing generator 13 shown in FIG. 1 receives the bit line activating signal BLSZ, and activates the word line activating signal WLSZ for a predetermined period (FIG. 3(h)). The main-word decoder 17 receives the word line activating signal WLSZ, and activates the word line signal WLZ (FIG. 3(i)). Due to the activation of the word line signal WLZ, the data retained in the memory cell 21 are output to the bit lines BL and /BL in the form of a weak signal (FIG. 3(j)).
The SA activating timing generator 14 receives the word activating signal WLSZ, and activates the sense amplifier activating timing signal BLEZ (FIG. 3(k)). The sense amplifier controller 18 receives the sense amplifier activating timing signal BLEZ, and activates the sense amplifier activating signals LEX and LEZ (FIG. 3(1)). In response to the sense amplifier activating signals LEX and LEZ, the sense amplifier 20 is activated to amplify the weak signal output to the bit lines BL and /BL.
The CL activating timing generator 15 receives the sense amplifier activating timing signal BLEZ, and activates the column line activating signal BCLZ for a predetermined period (FIG. 3(m)). The column decoder 19 receives the column line activating signal BCLZ, and activates the column line signal CLZ for a predetermined period (FIG. 3(n)). Due to the activation of the column line signal CLZ, the common data signal CDB0Z is supplied through the complementary data signals LDBX and LDBZ to the bit lines BL and /BL, and written in the memory cell 21 (FIG. 3(o)). Meanwhile, the common data signal CDB1Z is supplied through the complementary data signals LDBX and LDBZ to other bit lines BL and /BL, and written in another memory cell 21. In other words, the serially-input data signals DQ are written in the memory cells 21 in the form of parallel data. Here, if the weak signal output from a memory cell 21 is inverse in logic from the data signals LDBX, LDBZ, then a signal inverting operation is required.
Incidentally, in synchronization with the seventh clock signal CLK from the reception of the write command WR, a next command signal (write command WR) is accepted. That is, in this example, the number of clocks required for one write operation is seven (latency=7).
The RASZ generator 8 receives the self-precharging signal SPRZ (not shown) output from the CL activating timing generator 15, and inactivates the basic signal BRASZ (FIG. 3(p)). The word line activating timing generator 13 receives the basic signal BRASZ, and activates the word line inactivating signal WLRZ for a predetermined period (FIG. 3(q)). The main-word decoder 17 receives the word line inactivating signal WLRZ, and inactivates the word line signal WLZ (FIG. 3(r)). Due to the inactivation of the word line signal WLZ, the memory cell 21 is closed to retain the written data.
The SA activating timing generator 14 receives the word line inactivating signal WLRZ, and inactivates the sense amplifier activating timing signal BLEZ (FIG. 3(s)). The sense amplifier controller 18 receives the sense amplifier activating timing signal BLEZ, and inactivates the sense amplifier activating signals LEX and LEZ (FIG. 3(t)). Due to the inactivation of the sense amplifier activating signals LEX and LEZ, the sense amplifier 20 terminates its amplifying operation.
The BLT activating timing generator 12 receives the word line inactivating signal WLRZ, and activates the bit line inactivating signal BLRZ for a predetermined period (FIG. 3(u)). The BLT generator 16 receives the bit line inactivating signal BLRZ, activates the bit line controlling signal BLTX, and activates the bit line controlling signal BRSX (FIG. 3(v)). Due to the activates of the bit line controlling signal BLTX, the bit lines BL and /BL shown to the side closer to the memory cell 21 in FIG. 2 are equalized. The bit lines BL and /BL on the side opposite from the memory cell 21 are released from equalization, and connected to the sense amplifier 20. The activation amplifier 20. The [inactivation] activation of the bit line controlling signal BRSX precharges the bit lines BL and /BL.
Then, the above-described operations are repeated to perform write operations consecutively.
FIG. 4 shows the timing of performing the read operation after the write operation. In the write operation, the circuits operate at the same timing as shown in FIG. 3 described above. However, it needs to operate the memory core unit 4 in accordance with the acceptance of the data signals DQ in the write operation. On this account, the memory core unit 4 is operated by activating the bit line activating signal BLSZ, the word line activating signal WLSZ, and the like in synchronization with the activation of the write switching signal WSWZ after accepting the two-bit data signals DQ as internal data signals DI0 and DI1. That is, the memory core unit 4 delays in starting an operation in the write operation, compared to in the read operation. Accordingly, in this example, ten clocks are needed for the memory core unit 4 to prevent its controls for write and read operations from overlapping with each other. The number of clocks (the latency) required for each operation depends on the clock signal frequency.
In the read operation after the write operation, the input buffer 6 shown in FIG. 1 accepts a read command RD at the rise of the internal clock signal ICLKZ. The command decoder 7 receives the internal command signal ICMD, and activates the command activating signal ACTZ (FIG. 4(a)). The RASZ generator 8 receives the command activating signal ACTZ and activates the basic signal BRASZ (FIG. 4(b)). The BLT activating timing generator 12 receives the basic signal BRASZ, and activates the bit line activating signal BLSZ (FIG. 4(c)).
Subsequently, the same timing as that in a write operation is used to activate/inactivate the bit line controlling signals BLTX and BLTZ, the bit line controlling signal BRSX, the word line signal WLZ, the sense amplifier activating signals LEX and LEZ, and the column line signal CLZ, whereby the read operation is executed.
In read operations, the weak signal output from the memory cell 21 to the bit lines BL and /BL due to the activation of the word line signal WLZ is just amplified as read data. Therefore, the data are not inverted during read operations.
The signal amplified is transferred as the common data signal CDB0Z (FIG. 4(d)). The transferred signal is output as the data signal DQ in synchronization with the seventh clock signal CLK from the acceptance of the read command RD (FIG. 4(e)). Similarly, the signal amplified on the other bit lines BL and /BL is transferred as the common data signal CDB1Z, and output as the data signal DQ in synchronization with the eighth clock signal CLK from the acceptance of the read command RD.
As discussed above, the write operation being executed before a read operation requires ten clocks, three clocks more than usual.
For example, when a system equipped with FCRAMs repeats a write operation and a read operation alternately, a problem arises in that the entire system takes more processing time.
In addition, the memory core unit 4 supplies the same controlling timing to both write and read operations. Therefore, in a write operation, the weak signal output from the memory cell 21 is amplified by the sense amplifier 20 before write data are supplied to the bit lines BL and /BL. This requires a data inverting operation, thereby causing a problem of lengthening write time.
Meanwhile, for the sake of reducing the amplifying time, a sense amplifier 200 shown in FIG. 5 has been proposed as a substitute for the sense amplifier 20.
In this sense amplifier 200, the sources of pMOSs 200a and 200b in the respective CMOS inverters are connected with a pMOS 200c for establishing connection to a power supply line VII and a pMOS 200d for establishing connection to a power supply line VDD. The power supply line VDD is higher in voltage than the power supply line VII. The gate of the pMOS 200d receives a sense amplifier activating signal LEPX. The sense amplifier activating signals LEX, LEZ, and LEPX are generated by a sense amplifier controller (not shown). The other circuit configuration is the same as that of the sense amplifier 20 described above.
FIG. 6 shows the read amplifying operation of this sense amplifier 200.
Initially, the word line signal WLZ is activated, whereby a weak signal, which is the read data from the memory cell, is output to the bit lines BL and /BL. Then, the sense amplifier controller (not shown) activates the sense amplifier activating signals LEZ and LEPX. Due to the activation of the sense amplifier activating signals LEZ and LEPX, the slight voltage difference between the bit lines BL and /BL is amplified with its lower voltage toward the ground voltage VSS and its higher voltage toward the power supply voltage VDD (an overdrive period). Then, the sense amplifier controller inactivates the sense amplifier activating signal LEPX, and activates the sense amplifier activating signal LEX. By turning on the pMOS 200c shown in FIG. 5, the higher voltage is lowered to the power supply voltage VII. Since the higher voltage is boosted toward the power supply voltage VDD, the amplifying speed in the read operation is higher as compared to that of ordinary sense amplifiers (the chain line in the diagram).
FIG. 7 shows the write amplifying operation of the sense amplifier 200.
Initially, the word line signal WLZ is activated, whereby a weak signal irrelevant to the write data is output from the memory cell. Then, the sense amplifier controller (not shown) activates the sense amplifier activating signals LEZ and LEPX. Due to the activation of the sense amplifier activating signals LEZ and LEPX, the weak signal across the bit lines BL and /BL is amplified with its low-level side toward the ground voltage VSS and its high-level side toward the power supply voltage VDD. Subsequently, due to the activation of the column line signal CLZ, the write data is supplied to the bit lines BL and /BL and the weak signal amplified is inverted. Since the amplification level of the weak signal becomes greater than the amplification level in ordinary sense amplifiers (the chain line in the diagram), the time needed for data inversion becomes longer. This causes a problem of lengthening write time.
An object of the present invention is to provide a semiconductor integrated circuit which can reduce the time necessary for writing data in a memory cell.
According to one of the aspects of the semiconductor integrated circuit in the present invention, a controlling signal generating unit generates a bit line controlling signal, a word line signal, a sense amplifier activating signal, and a column line signal.
The bit line controlling signal activates a resetting circuit which resets a bit line. The word line signal controls the connection between a memory cell and the bit line which transmits data to the memory cell. The sense amplifier activating signal activates a sense amplifier which amplifies data transmitted to the bit line. The column line signal activates a column switch which transmits data to the bit line.
The controlling signal generating unit activates predetermined signal(s) among the word line signal, the sense amplifier activating signal, the bit line controlling signal, and the column line signal at the start of a write operation. The controlling signal generating unit activates the remaining signal(s) after receiving write data.
Since the predetermined signal(s) is/are activated without receiving write data, it is possible to make the activating timing of the remaining signal(s) earlier. This consequently reduces the time necessary for a write operation.
According to another aspect of the semiconductor integrated circuit in the present invention, a serial/parallel conversion circuit accepts serial data to be written in the memory cell and converts it into parallel data. The controlling signal generating unit activates the aforesaid remaining signal(s) in synchronization with an accepting signal used for the serial/parallel conversion circuit. This reliably activates the remaining signal(s) without generating a new controlling signal.
According to yet another aspect of the semiconductor integrated circuit in the present invention, the first controlling circuit in the controlling signal generating unit activates the first activating signal in synchronization with an accepting signal in a write operation. The first controlling circuit of the controlling signal generating unit keeps activating the first activating signal throughout a read operation. The second controlling circuit in the controlling signal generating unit generates the second activating signal in synchronization with the start of a write operation and the start of a read operation. A detecting circuit detects the activation of both the first and the second activating signals. Then, the controlling signal generating unit generates the aforesaid remaining signal(s) by using the detection result of the detecting circuit.
This allows easy generation of the remaining signal(s) at respective predetermined timings in write and read operations.
According to another aspect of the semiconductor integrated circuit in the present invention, the first controlling circuit in the controlling signal generating unit activates the first activating signal in synchronization with the accepting signal in a write operation. In a read operation, the second controlling circuit in the controlling signal generating unit activates the second activating signal in synchronization with the start of the read operation. The detecting circuit detects the activation either the first or the second activating signal. Then, the controlling signal generating unit generates the aforesaid remaining signal(s) by using the detection result from the detecting circuit.
This allows easy generation of the remaining signal(s) at respective predetermined timings in write and read operations.
According to another aspect of the semiconductor integrated circuit in the present invention, the column switch is activated earlier in a write operation than it would in a read operation. This makes it possible to supply write data to the bit line before or immediately after the amplification of a weak signal output from a memory cell. When a logic level of the weak signal differs from that of the write data, the data need to be inverted. However, the amplification of the weak signal is minimized as described above so that the time required for the inverting operation is reduced. This consequently reduces the time necessary for a write operation.
According to another aspect of the semiconductor integrated circuit in the present invention, the sense amplifier has an overdriving function of using a higher voltage for a predetermined period at the start of amplification. In a write operation, the activation of the column switch is started before the initiation of the overdriving. On this account, write data are supplied to the bit line before the amplification of a weak signal by the overdriving. This minimizes the amplification of the weak signal irrelevant to the write data by the overdriving. As a result, it is possible to have the overdriving well functioning in a read operation while precluding the overdriving in a write operation. This consequently reduces the time necessary for a write operation without increasing the time required for a read operation.
According to another aspect of the semiconductor integrated circuit in the present invention, the predetermined signal(s) can be activated without the acceptance of write data, resulting in making the activating timing of the remaining signal(s) earlier. This consequently reduces the time necessary for a write operation.